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1 typical operating circuit 19-6400; rev 0; 7/12 ordering information appears at end of data sheet. for related parts and recommended products to use with this part, refer to www.maxim-ic.com/MAX71020.related . general description the MAX71020 is a single-chip, analog front-end to be used in high-performance revenue meters. it contains the compute engine found in maxims fourth-generation meter soc and an improved adc, and interfaces to the host microcontroller of choice over a spi interface. the MAX71020 comes in a 28-pin tssop package. features s 0.1% accuracy over 2000:1 current range s exceeds iec 62053/ansi c12.20 standards s two differential current sensor inputs s two voltage sensor inputs s selectable gain of 1 or 9 for one current input to support a shunt s high-speed wh/varh pulse outputs with programmable width s up to four pulse outputs with pulse count s four-quadrant metering s digital temperature compensation s independent 32-bit compute engine s 45hz to 65hz line frequency range with same calibration s phase compensation (10) s four multifunction dio pins s spi interface s -40c to +85c industrial temperature range s 28-pin tssop lead(pb)-free package iap va ibp xin oscillator/p ll xout 9.8304mhz gnda gndd line neutral load mux and adc compute engine power-fault comparator regulator ct power supply temperature sensor v ref neutral ian ibn dio, pulses spi interface host shunt line vb v 3p3a v 3p3sys MAX71020 resistor- divider line note: this system is referenced to line MAX71020 single-chip electricity meter afe for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxims website at www.maxim-ic.com.
2 MAX71020 single-chip electricity meter afe (all voltages with respect to gnda.) voltage and current supplies and ground pins v 3p3sys , v 3p3a .................................................. -0.5v to +4.6v gndd ................................................................... -0.1v to +0.1v analog input pins iap, ian, ibp, ibn, va, vb ............................ (-10ma to +10ma), (-0.5v to (v 3p3a + 0.5v)) xin, xout ......................... (-10ma to +10ma), (-0.5v to +3.0v) digital pins inputs .................................... (-10ma to +10ma), (-0.5v to +6v) outputs ............ (-10ma to +10ma), (-0.5v to (v 3p3sys + 0.5v)) temperature and esd stress operating junction temperature (peak, 100ms) .............. 140c operating junction temperature (continuous) ................. 125c storage temperature range ............................ -45c to +165c esd stress on all pins .............................................. 4kv, hbm lead temperature (soldering, 10s) .................................. 300c soldering temperature (reflow) ...................................... +250c tssop junction-to-ambient thermal resistance ( q ja ) .......... 78c/w junction-to-case thermal resistance ( q jc ) ............... 13 n c/w absolute maximum ratings note 1: package thermal resistances were obtained using the method described in jedec specification jesd51-7, using a four- layer board. for detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial . stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional opera - tion of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. package thermal characteristics (note 1) electrical characteristics parameter conditions min typ max units recommended operating conditions v 3p3sys and v 3p3a supply voltage precision metering operation 3.0 3.6 v digital operation 2.8 3.6 operating temperature -40 +85 n c input logic levels digital high-level input voltage (v ih ) 2 v digital low-level input voltage (v il ) 0.8 v input pullup current (i il ) resetz v v3p3sys = 3.6v, v in = 0v 41 78 115 f a input pullup current (i il ) other digital inputs v v3p3sys = 3.6v, v in = 0v -1 0 +1 f a input pulldown current (i ih ) all pins vin = v3p3sys -1 0 +1 f a output logic levels digital high-level output voltage (v oh ) i load = 1ma v 3p3sys - 0.4 v i load = 15ma (note 2) v 3p3sys - 1.1 digital low-level output voltage (v ol ) i load = 1ma 0 0.4 v i load = 15ma (note 2) 0 0.96 temperature monitor tnom (nominal value at 22 n c) v v3p3a = 3.3v 956 lsb
3 MAX71020 single-chip electricity meter afe electrical characteristics (continued) parameter conditions min typ max units temperature measurement equation temp = 0.33 x stemp + 21.77 n c temperature error (note 2) t a = -40 n c to +85 n c -6 +6 n c t a = -20 n c to +60 n c -4.8 +4.8 duration of temperature measurement after setting temp_start temp_per = 0 15 60 ms supply current performance specifications v 3p3a + v 3p3sys current (note 2) v v3p3a = v v3p3sys = 3.3v, ce_e = 1, adc_e = 1 4.3 ma internal power-fault comparator specifications overall response time 100mv overdrive, falling 20 200 s 100mv overdrive, rising 8 200 falling threshold 3.0v comparator 2.83 2.93 3.03 v 2.8v comparator 2.75 2.81 2.89 v difference 3.0v and 2.8v comparators 50 136 220 mv hysteresis (rising threshold - falling threshold) 3.0v comparator, t a = +22 n c 17 45 74 mv 2.8v comparator, t a = +22 n c 15 42 70 pll performance specifications pll power-up settling time v v3p3a = 0 to 3.3v step, measured from first edge of mck 75 s pll_fast settling time v v3p3a = 3.3v, pll_fast rise 10 s v v3p3a = 3.3v, pll_fast fall 10 pll lock frequency at xout v v3p3a = 3.3v, mck frequency error < 1% 7 9.8 13 mhz vref performance specifications vref output voltage, vref (22) t a = +22 n c 1.200 1.205 1.210 v vref power-supply sensitivity ( d v ref / d v 3p3a ) v 3p3a = 3.0v to 3.6v -1.5 +1.5 mv/v vnom definition vnom(t) = vref(22) + tc1(t - 22) + tc2(t - 22) 2 v vnom temperature coefficient tc1 29.32 - 1.05 x trimt v/ n c vnom temperature coefficient tc2 -0.56 - 0.004 x trimt v/ n c 2 vref(t) deviation from vnom(t): (note 2) -40 +40 ppm/ n c adc converter performance specifications recommended input range (with respect to gnda) va, vb, ibp, ibn -250 +250 mv peak 6 vref(t) - vnom(t)10 vnom(t) 62
4 MAX71020 single-chip electricity meter afe electrical characteristics (continued) parameter conditions min typ max units recommended input range (with respect to gnda) iap, ian (preamplifier enabled) -27.78 +27.78 mv peak input impedance, no preamplifier f in = 65hz 50 100 k i adc gain error vs percentage power- supply variation v in = 200mv peak, 65hz v v3p3a = 3.0v, 3.6v 81 ppm/% input offset iap = ian = gnda -10 +10 mv total harmonic distortion at 250mvpk v in = 55hz, 250mvpk, 64kpts fft, blackman harris window -85 db total harmonic distortion at 20mvpk v in = 55hz, 20mvpk, 64kpts fft, blackman harris window -85 db lsb size (lsb values do not include the 9-bit left shift at the ce input) v in = 55hz, 20mvpk, 64kpts fft, blackman-harris window, 10mhz ckadc firlen = 15 120.46 nv firlen = 14 146.20 firlen = 13 179.82 firlen = 12 224.59 firlen = 11 285.54 firlen = 10 370.71 digital full scale v in = 55hz, 400mvpk, 10mhz ckadc firlen = 15 2621440 lsb firlen = 14 2160000 firlen = 13 1756160 firlen = 12 1406080 firlen = 11 1105920 firlen = 10 851840 preamplifier performance specifications differential gain, (v in = 28mv differential) t a = +25 n c, v v3p3a = 3.3v, pre_e = 1, diff0_e = 1 8.9 v/v differential gain (v in = 15mv differential) gain variation vs. v 3p3 (v in = 28mv differential) v v3p3a = 3.0v, 3.6v -72 ppm/% gain variation vs. temperature (v in = 28mv differential) (note 4) t a = -40 n c to +85 n c -45 ppm/ n c 6 pk in 10 nout 357nv v 100 v3p3a 3.3 ? ?
5 MAX71020 single-chip electricity meter afe electrical characteristics (continued) note 2: guaranteed by design, not production tested. note 3: v 3p3sys and v 3p3a must be connected together. note 4: agnd and dgnd must be connected together. parameter conditions min typ max units phase shift (v in = 28mv differential) (note 2) t a = +25 n c , v v3p3a = 3.3v 0 8 m n preamplifier input current (i adc0 ) pre_e = 1, diff0_e = 1, iadc0 = iadc1 = v 3p3a 9 15 20 f a preamplifier input current (i adc1 ) preamplifier and adc total harmonic (v in = 28mv differential) t a = +25 n c; v v3p3a = 3.3v, pre_e = 1, diff0_e = 1 -80 db preamplifier and adc total harmonic distortion (v in = 15mv differential) t a = +25 n c; v v3p3a = 3.3v, pre_e = 1, diff0_e = 1 -85 db spi slave timing specifications spi setup time spi_di to spi_ck rise 10 ns spi hold time spi_clk rise to spi_di 10 ns spi output delay spi_clk fall to spi_d0 40 ns spi recovery time spi_csz fall to spi_clk 10 ns spi removal time spi_clk to spi_csz rise 15 ns spi clock high 40 ns spi clock low 40 ns spi clock frequency 10 mhz spi transaction space (spi_csz rise to spi_csz fall) 1 f s resetz timing reset pulse width following power-on 1 ms at all other times 5 f s reset pulse rise time (note 2) 1 f s voltage monitor nominal value at +22 n c (vnom) v v3p3a = 3.3v 130 lsb voltage measurement equation v v3p3 (calc) = 3.29v + (bsense C 130) x 0.025v + stemp x 242v voltage error -4 +4 % v3p3 v3p3 v (calc) 100 - 1 v ?? ?? ??
6 MAX71020 single-chip electricity meter afe recommended external components pin configuration name from to function value units c1 v 3p3a gnda bypass capacitor for 3.3v supply r 0.1 20% f csys v 3p3sys gndd bypass capacitor for v 3p3sys r 1.0 30% f c1p8 v dd gndd bypass capacitor for v1p8 regulator 0.1 20% f xtal xin xout at cut crystal specified for 18pf load 9.8304 mhz cxs xin gnda load capacitor values for crystal depend on crystal specifications and board parasitics. nominal values are based on 4pf board capacitance and include an allowance for chip capacitance. 32 10% pf cxl xout gnda 32 10% pf top view MAX71020 25 4x in ibn 26 3x ou t v 3p3a 27 2 te st 0 gnda 28 1 + vb va 22 7 di o0 /w pu ls e iap 23 6 v dd ian 21 8 di o1 /v pu ls e test 20 9 di o2 /x pu ls e resetz 19 10 in tz v pp 18 11 n .c. dio3/ypulse 17 12 n .c. gndd 16 13 sp i_c lk spi_csz 24 5 v 3p3s ys ibp 15 14 sp i_d i spi_do tssop
7 MAX71020 single-chip electricity meter afe pin description (pin types: p = power, o = output, i = input, i/o = input/output. the circuit number denotes the equivalent circuit, as specified under figure 1). pin name type circuit description power and ground pins 2 gnda p analog ground. gnda should be connected directly to the ground plane. 3 v 3p3a p analog power supply. a 3.3v power supply should be connected to v 3p3a . v 3p3a must be the same voltage as v 3p3sys . 12 gndd p digital ground. gndd should be connected directly to the ground plane. 23 v dd o output of the 1.8v regulator. a 0.1f bypass capacitor to ground should be connected to this pin. 24 v 3p3sys p system 3.3v supply. v 3p3sys should be connected to a 3.3v power supply. analog pins 7, 6 iap, ian i 6 differential or single-ended line current-sense inputs. these pins are voltage inputs to the internal adc. typically, these pins are connected to the outputs of current sensors. unused pins must be tied to gnda . 5, 4 ibp, ibn 1, 28 va, vb i 6 line voltage sense inputs. va/vb are voltage inputs to the internal adc. typically, the pins are connected to the outputs of resistor- dividers. unused pins must be tied to gnda . 25 xin i 8 crystal inputs. a 9.8304mhz crystal should be connected to xin and xout. 26 xout o digital pins 22 dio0/wpulse i/o 3, 4 multiple-use pins. configurable as dio. alternative functions with proper selection of associated registers are: dio0 = wpulse dio1 = vpulse 21 dio1/vpulse 20 dio2/xpulse 11 dio3/ypulse 8, 27 test, test0 i 3 connect to gndd 9 resetz i 3 active-low reset 13 spi_csz i 3 spi interface 14 spi_do o 4 15 spi_di i 3 16 spi_clk i 3 19 intz o 4 active-low interrupt request other pin 10 v pp i connect to gndd
8 MAX71020 single-chip electricity meter afe figure 1. i/o equivalent circuits di gi ta l i nput pi n an al og in put pi n di gi ta l ouput pi n cm os i npu t gndd v 3p3sys di gi ta l in pu t eq ui vale nt ci rc ui t ty pe 3 analog in pu t eq ui vale nt ci rc ui t ty pe 6: ad c in put cm os outp ut di gi ta l outpu t eq ui vale nt ci rc ui t ty pe 4 gndd gndd v 3p3sys v 3p3sys v 3p3sys to mux gnda v 3p3sys osc illator pi n os c illa to r eq ui vale nt ci rc ui t ty pe 8: os c illat or i/o to oscilla to r gnda gnda
9 MAX71020 single-chip electricity meter afe functional block diagram MAX71020 dc modulator fi r de ci ma to r preamplifier input multiplexer start iap gnda v 3p3a ian voltage regulator v dd ibp ibn vb va ckce 20mhz, 5mhz mux_sync xin xout mck mu lt ip le xer co nt ro l vref crystal oscillator 9.83mhz master clock pll v ref clock generator temp sense vref power status ce 32 -b it co mput e en gine vstat resetz v3p3a 2 ck a dc (1 0m hz , 5m hz , 2.5mh z, 1.25 mh z) gn dd v 3p3sys spi intz spi _c sz parity err spi _d i spi _d o spi _clk wpulse d10_wpulse intz d11_vpulse d12_xpulse d13_ypulse xfer_busy vstat 2 vpulse xpulse ypulse 1.8v to logic pulse control io_ctrl
10 MAX71020 single-chip electricity meter afe hardware description hardware overview the MAX71020 energy meter analog front-end (afe) integrates all primary functional blocks required to imple - ment a solid-state residential electricity meter. included on the chip are: an analog front-end (afe) featuring a 22-bit second- order sigma-delta adc an independent 32-bit digital computation engine (ce) to implement dsp functions a precision voltage reference (vref) a temperature sensor for digital temperature compensation four i/o pins a zero-crossing interrupt resistive shunt and current transformers are supported a spi slave for connection to a host microcontroller in a typical application, the 32-bit compute engine (ce) of the MAX71020 sequentially processes the samples from the voltage inputs on analog input pinsand performs calculations to measure active energy (wh) and reactive energy (varh), as well as a 2 h, and v 2 h for four-quadrant metering. these measurements are then accessed by the host microcontroller. in addition to the temperature-trimmed ultra-precision voltage reference, the on-chip digital temperature com - pensation mechanism includes a temperature sensor and associated controls for correction of unwanted temperature effects on measurement, e.g., to meet the requirements of ansi and iec standards. temperature-dependent external components such as crystal oscillator, resistive shunts, current transformers (cts) and their corresponding signal conditioning circuits can be characterized and their correction factors can be programmed to produce electricity meters with excep - tional accuracy over the industrial temperature range. communications with the host is conducted over a spi interface. the communications protocol between the host and the MAX71020 provides a redundant information transfer ensuring the correctness of commands trans - ferred from the host to the afe, and of data transferred from the afe to the host. in addition, the MAX71020 has one pin dedicated as an interrupt output to the host. in this way, the MAX71020 notifies the host of asynchronous events. analog section signal input pins the MAX71020 has four analog inputs: two single-ended inputs for voltage measurement, and two differential inputs for current measurement. iap, ian, ibp, and ibn pins are current sensor inputs. the differential inputs feature preamplifiers with a select - able gain of 1 or 9, and are intended for direct connection to a shunt resistor sensor or a current transformer (ct). the voltage inputs in the MAX71020 are single-ended, and are intended for sensing the line voltage. these single-ended inputs are referenced to the gnda pin. all analog signal input pins measure voltage. in the case of shunt current sensors, currents are sensed as a voltage drop in the shunt resistor sensor. in the case of current transformers (ct), the current is measured as a voltage across a burden resistor that is connected to the secondary winding of the ct. meanwhile, line voltages are sensed through resistive voltage-dividers. voltage inputs are single-ended and their common return is the gnda pin. some versions of the device implement a preamplifier with a fixed gain of 9 to enhance performance when using sensors with a low-amplitude output (for example, current shunts). when using a device with the preampli - fier enabled, you must ensure that the input amplitude is no greater than 27.78mv peak. input multiplexer the input multiplexer sequentially applies the input signals from the analog input pins to the input of the adc. one complete sampling sequence is called a multiplexer frame. the ibp-ibn differential input may be used to sense the neutral current, and vb may be optionally used to sense a second voltage channel.this configuration implies that the multiplexer applies a total of four inputs to the adc. for this configuration, the multiplexer sequence is as shown in figure 1 . in this configuration iap-ian, ibp-ibn, va and vb are sampled. the physical current sensor for the neutral current measurement and the voltage sensor for vb may be omitted if not required.
11 MAX71020 single-chip electricity meter afe table 1. adc input configuration figure 2. states in a multiplexer frame for a standard single-phase application with tamper sen - sor in the neutral path, two current inputs are configured for differential mode, using the pin pairs iap-ian and ibp-ibn. in the MAX71020, the system uses two locally connected current sensors via iap-ian and ibp-ibn and configured as differential inputs. the va pin is typically connected to the phase voltage via resistor-dividers. the MAX71020 adds the ability to sample a second phase voltage (applied at the vb pin), which makes it suitable for meters with two voltage and two current sen - sors, such as meters implementing equation 2 for dual- phase operation (p = va x ia + vb x ib). table 1 summarizes the afe input configuration. delay compensation when measuring the energy of a phase (i.e., wh and varh) in a service, the voltage and current for that phase must be sampled at the same instant. otherwise, the phase difference, , introduces errors. delay delay t 360 t f 360 t = = ?? where f is the frequency of the input signal, t = 1/f and t delay is the sampling delay between current and voltage. traditionally, sampling is accomplished by using two adcs per phase (one for voltage and the other one for current) controlled to sample simultaneously. maxims teridian? single-converter technology?, however, exploits the 32-bit signal processing capability of its ce to implement constant delay allpass filters. the allpass filter corrects for the conversion time difference between the voltage and the corresponding current samples that are obtained with a single multiplexed adc. the constant delay allpass filter provides a broadband delay 360 n - , which is precisely matched to the differ - ence in sample time between the voltage and the current of a given phase. this digital filter does not affect the amplitude of the signal, but provides a precisely con - trolled phase response. the adc multiplexer samples the current first, immedi - ately followed by sampling of the corresponding phase voltage, thus the voltage is delayed by a phase angle relative to the current. the delay compensation imple - mented in the ce aligns the voltage samples with their corresponding current samples by first delaying the cur - rent samples by one full sample interval (i.e., 360 n ), then routing the voltage samples through the allpass filter, thus delaying the voltage samples by 360 n - , resulting in the residual phase error between the current and its corre - sponding voltage of - . the residual phase error is neg - ligible, and is typically less than 0.0015 n at 100hz, thus it does not contribute to errors in the energy measurements. adc preamplifier the adc preamplifier is a low-noise differential amplifier with a fixed gain of 9 available on the iap and ian current- sensor input pins. it is provided only in versions of the MAX71020 afe configured for use with current shunts. teridian is a trademark and single converter technology is a registered trademark of maxim integrated products, inc. pin comment iap the adc results are stored in register ia . ian ibp the adc results are stored in register ib . ibn va the adc result is stored in register va . vb the adc result is stored in register vb . multiplexer frame mux div = 4 conversions settle s ck32 mux state cross mux_sync 0 ia va ib vb 12 3s 0
12 MAX71020 single-chip electricity meter afe analog-to-digital converter (adc) a single second-order delta-sigma adc digitizes the voltage and current inputs to the device. the resolution of the adc is dependent on several factors. initiation of each adc conversion is automatically con - trolled by logic internal to the MAX71020. at the end of each adc conversion, the fir filter output data is stored into the register determined by the multiplexer selection. fir data is stored lsb justified, but shifted left 9 bits. fir filter the finite impulse response filter is an integral part of the adc and it is optimized for use with the multiplexer. the purpose of the fir filter is to decimate the adc output to the desired resolution. at the end of each adc conver - sion, the output data is stored into the register deter - mined by the multiplexer selection. voltage references a bandgap circuit provides the reference voltage to the adc. since the vref bandgap amplifier is chopper stabilized, the dc offset voltage, which is the most signifi - cant long-term drift mechanism in the voltage references (vref), is automatically removed by the chopper circuit. digital computation engine (ce) the ce, a dedicated 32-bit signal processor, performs the precision computations necessary to accurately mea - sure energy. the ce calculations and processes include: multiplication of each current sample with its associ - ated voltage sample to obtain the energy per sample (when multiplied with the constant sample time) frequency-insensitive delay cancellation on all four channels (to compensate for the delay between samples caused by the multiplexing scheme) 90 phase shifter (for var calculations) pulse generation monitoring of the input signal frequency (for frequency and phase information) monitoring of the input signal amplitude (for sag detection) scaling of the processed samples based on calibra - tion coefficients scaling of samples based on temperature compensa - tion information gain and phase compensation meter equations the MAX71020 provides hardware assistance to the ce in order to support various meter equations. this assis - tance is controlled through register equ[2:0] (equation assist). the compute engine (ce) firmware implements the equations listed in table 2 . equ[2:0] specifies the equation to be used based on the meter configuration and on the number of phases used for metering. pulse generators the MAX71020 provides up to four pulse generators, vpulse, wpulse, xpulse, and ypulse, as well as hardware support for the vpulse and wpulse pulse generators. the pulse generators are used to output ce status indicators and energy usage. the polarity of the pulses may be inverted with control bit pls_inv. when this bit is set, the pulses are active-high, rather than the more usual active-low. pls_inv inverts all four pulse outputs. the function of each pulse generator is determined by the ce code. the MAX71020 provides a mains zero- crossing indication on xpulse and voltage sag detec - tion on ypulse. a common use of the zero-crossing pulses is to generate interrupt in order to drive rtc software in places where the mains frequency is sufficiently accurate to do so and also to adjust for crystal aging. a common use for the sag pulse is to generate an interrupt that alerts the host processor when mains power is about to fail, so that the host processor can store accumulated energy and other data to eeprom before the supply voltage actually drops. table 2. inputs selected in multiplexer cycles equ description wh and varh formula element 0 element 1 0 1 element, 2w, 1 j with neutral current sense va ? ia va ? ib 1 1 element, 3-w, 1 j va(ia-ib)/2 va ? ib/2 2 2 element, 3-w va ? ia vb ? ib
13 MAX71020 single-chip electricity meter afe xpulse and ypulse pulses generated by the ce may be exported to the xpulse and ypulse pulse output pins. pins d2 and d3 are used for these pulses, respectively. the xpulse and ypulse outputs can be updated once on each pass of the ce code. see the ce interface description section for details. vpulse and wpulse by default, wpulse and vpulse are negative pulses (i.e., low level pulses, designed to sink current through an led). pls_maxwidth[7:0] determines the maximum negative pulse width t max in units of ck_fir clock cycles based on the pulse interval t i according to the formula: t max = (2 x pls_maxwidth[7:0] + 1) x t i t i is based on an internal value that determines the pulse interval and the adc clock, both of which are determined by the particular characteristics of the compute engine. in the MAX71020, the default value for t i is 65.772s, but this value changes in customized versions of this part. if pls_maxwidth = 255 no pulse-width checking is per - formed, and the pulses default to 50% duty cycle. t max is typically programmed to 10ms (t max = 76), which works well with most calibration systems. the polarity of the pulses may be inverted with the control bit pls_inv. when pls_inv is set, the pulses are active- high. the default value for pls_inv is zero, which selects active-low pulses. the wpulse and vpulse pulse generator outputs are available on pins d0/wpulse and d1/vpulse, respectively. temperature sensor the MAX71020 includes an on-chip temperature sen - sor for determining the temperature of its bandgap reference. the primary use of the temperature data is to determine the magnitude of compensation required to offset the thermal drift in the system for the compensation of current, voltage, and energy measurement. see the metrology temperature compensation section. the temperature sensor is awakened on command from the host microcontroller by setting the temp_start control bit. the host microcontroller must wait for the temp_start bit to clear before reading stemp[15:0] and before setting the temp_start bit once again. the result of the temperature measurement can be read from the stemp[15:0] register. the 16-bit value is in twos complement form and ranges from -1024 to +1023 (decimal). the sensed temperature can be computed from the 16-bit stemp[15:0] reading using the following formula: temp ( n c) = 0.325 x stemp + 22 an additional register, vsense[7:0], senses the level of supply voltage. table 4 shows the registers used for temperature measurement. digital i/o on reset or power-up, all dio pins are configured as high-impedance. dio pins can be configured indepen - dently by the host microcontroller by manipulating the d0, d1, d2, and d3 bit fields. table 3. pulse output function assignments table 4. temperature measurement registers output function xpulse pulse output on each zero crossing on voltage input ypulse pulse output when voltage sag detected vpulse pulse output when programmed varh consumption has occurred wpulse pulse output when programmed wh consumption has occurred name rst wk dir description tbyte_busy 0 0 r indicates that hardware is still writing the result. additional writes to this byte are locked out while it is one. write duration could be as long as 6ms.
14 MAX71020 single-chip electricity meter afe spi slave port the slave spi port communicates directly with the host microcontroller and allows it to read and write the device control registers. the interface to the slave port consists of the spi_csz, spi_clk, spi_di, and spi_do pins. spi transactions spi transactions are configured to provide immunity to electrical noise through redundancy in the command segment and error checking in the data field. the MAX71020 spi transaction is exactly 64 bits; transactions of any other length are rejected. each spi transaction has the following fields: a 24-bit setting packet, consisting of ? 11-bit address, msb first ? 1-bit direction (1 means read) ? 11-bit inverted address, msb first ? 1-bit inverted direction an 8-bit status, consisting of the following bits concerning the last transaction, starting from bit 7: ? 11-bit address, msb ? parity of the status byte (0 or 1 could be correct) ? fifo overflow status bit (1 means error) ? fifo underrun status bit (1 means error) ? read or write data parity (0 or 1 could be correct) (never both read and write; address is not included in the parity) ? address or direction mismatch error bit (1 means error) ? result of the spi_csz glitch detector (1 means error) ? a bit indicating whether or not the bit count was exactly 64 (1 means error). ? out of bounds address, most likely due to spi safe bit or the memory manager (1 means error). a 32-bit packet of data, msb first ? if extra clocks are provided at the end during a read, all zero is output and the status will continue to be updated, signaling an error. ? if extra clocks are provided at the end during a write, the write will be aborted and the status will be updated to signal an error. none of the fields above are optional. if an error is detected during the address or direction phase, no action will be taken. spi_do is high-z while spi_csz is high. spi safe mode will be supported, and spi will not be locked out of this bit during spi safe. a typical spi transaction is as follows. while spi_csz is high, the port is held in an initialized/reset state. during this state, spi_do is held in high-z state and all transitions on spi_clk and spi_di are ignored. when spi_csz falls, the port will begin the transaction on the first rising edge of spi_clk. as shown in table 5, a transaction consists of a 24-bit setting field, an 8-bit table 4. temperature measurement registers (continued) name rst wk dir description temp_per[1:0] 0 r/w sets the period between temperature measurements temp_per time 0 manual updates (see temp_start description ) 1 every accumulation cycle 2 continuous temp_start 0 r/w temp_per[1:0] must be zero in order for temp_start to function. if temp_per[1:0] = 0, then setting temp_start starts a temperature measurement. hardware clears temp_start when the temperature measurement is complete. the host microcontroller must wait for temp_start to clear before reading stemp[10:0] and before setting temp_start again. stemp[15:0] r the result of the temperature measurement vsense[7:0] r the result of voltage sense reading: v 3p3sys = vsense[7:0] /42.7
15 MAX71020 single-chip electricity meter afe status, and a 32-bit data word. the transaction ends when spi_csz is raised. note that the status byte indicates the status of the previ - ous spi transaction except for the status byte parity. spi safe mode sometimes it is desirable to prevent the spi interface from writing to arbitrary registers and possibly disturbing the ce operation. for this reason, the spi_safe mode is created. in this mode, all spi writes are disabled except to the word containing the spi_safe bit. this affords the host one more layer of protection from inadvertent writes. functional description theory of operation the energy delivered by a power source into a load can be expressed as: t 0 e v(t)i(t)dt = assuming phase angles are constant, the following for - mulae apply: p = real energy [wh] = v x a x cos x t q = reactive energy [varh] = v x a x sin x t s = apparent energy [vah] = 22 pq + for a practical meter, not only voltage and current ampli - tudes, but also phase angles and harmonic content may constantly change. thus, simple rms measurements are inherently inaccurate. a modern solid-state electricity meter ic such as the MAX71020 functions by emulating the integral operation above, i.e., it processes current and voltage samples through an adc at a constant fre - quency. as long as the adc resolution is high enough and the sample frequency is beyond the harmonic range of interest, the current and voltage samples, multiplied with the time period of sampling yield an accurate quan - tity for the momentary energy. summing the instanta - neous energy quantities over time provides very accurate results for accumulated energy. table 5. spi transaction (64 bits) figure 3. spi slave porttypical read and write operations 24-bit setting field 8-bit status 32-bit data address dir inv address inv dir status from previous transaction: status[7:0] data addr[10:0] rd addr_b[10:0] rd_b status parity fifo overrun fifo underrun data parity setting mismatch csb glitch bad ck cnt bad address data[31:0] serial read 11-bit address 0 a10 a9 a1 a0 a10 rd 10 11 22 23 24 31 32 47 48 63 01 01 12 22 32 43 13 24 74 86 3 d0 d1 d13 d14 d15 d16 d30 d31 st0 st6 st7 x 11-bit inverted address status byted ata [addr] rd (from host) spi_csz (from host) spi_clk (from host) spi_di (from am48) spi_do (from am48) spi_do (from host) spi_csz (from host) spi_clk (from host) spi_di serial write rd 11-bit address 11-bit inverted address status byted ata [addr] rd rd a9 a0 rd a10 a9 a1 a0 hi-z hi-z a10 rd d31 st7s t6 st0 d30 d16 d15 d14 d13 d1 d0 x x a9 a0 rd
16 MAX71020 single-chip electricity meter afe figure 4 shows the shapes of v(t), i(t), the instantaneous power and the accumulated energy resulting from 50 samples of the voltage and current signals over a period of 20ms. the application of 240vac and 100a results in an accumulation of 480ws (= 0.133wh) over the 20ms period, as indicated by the accumulated power curve. the described sampling method works reliably, even in the presence of dynamic phase shift and harmonic distortion. fault and reset behavior events at power-down power fault detection is performed by internal com - parators that monitor the voltage at the v 3p3a pin and also monitor the internally generated v dd pin voltage (1.8vdc). v 3p3sys and v 3p3a must be connected together at the pcb level, so that the comparators, which are internally connected only to the v 3p3a , are able to simultaneously monitor the common v 3p3sys and v 3p3a voltage. the following discussion assumes that v 3p3a and v 3p3sys are connected together at the pcb level. during a power failure, as v 3p3a falls, two thresholds are detected. the first threshold, at 3.0v, warns the host microcontroller that the analog modules are no longer accurate. the second threshold, at 2.8v, warns the host microcontroller that a serious reduction in supply voltage has occurred. otp reads may be affected. reset sequence when the MAX71020 receives a reset signal, either from the resetz pin or from the spi, it asynchronously halts what it was doing. it then clears ram and initializes con - figuration bits. an errant reset can occur during an esd event. if this happens, the host must be notified. this is accomplished by holding the intz output low until the host clears it. applications information sensor connection figure 5 to figure 8 show voltage-sensing resistive divid - ers, current-sensing current transformers (cts) and cur - rent-sensing resistive shunts and how they are connect - ed to the voltage and current inputs of the MAX71020. all input signals to the MAX71020 sensor inputs are voltage signals providing a scaled representation of either a sensed voltage or current. the analog input pins of the MAX71020 are designed for sensors with low source imped - ance. rc filters with resistance values higher than those implemented in the demo boards must not be used. refer to the demo board schematics for complete sensor input circuits and corresponding component values. figure 4. voltage, current, momentary and accumulated energy table 6. vstat[1:0] vstat[1:0] description 00 system power-ok. v v3p3a > 3.0v. analog modules are functional and accurate. 01 system power is low. 2.8v < v v3p3a < 3.0v. analog modules not accurate. 11 system power below 2.8v. ability to monitor power is about to fail. 15 10 5 -400 -300 -200 -100 0 100 200 300 400 500 -500 02 0 current [a] voltage [v] energy per interval [ws] accumulated energy [ws]
17 MAX71020 single-chip electricity meter afe figure 5. resistive voltage-divider (voltage sensing) figure 7. ct with differential input connection (current sensing) figure 6. ct with single-ended input connection (current sensing) figure 8. differential resistive shunt connections (current sensing) r in v in r out va gnda i in r burden v out noise filter iap gnda ct 1:n i out i in r burden v out iap ian ct 1:n bias network and noise filter gnda i out r shunt v out iap ian bias network and noise filter gnda
18 MAX71020 single-chip electricity meter afe figure 9. connecting the MAX71020 connecting the MAX71020 figure 9 shows a typical MAX71020 configuration. the iap-ian current channel may be directly connected to either a shunt resistor or a ct, while the ibp-ibn chan - nel is connected to a ct and is therefore isolated. this configuration implements a single-phase measurement with tamper-detection using one current sensor to mea - sure the neutral current. this configuration can also be used to create a split phase meter (e.g., ansi form 2s). iap va ibp xin oscillator/p ll xout 9.8304mhz gnda gndd line neutral load mux and adc compute engine power-fault comparator regulator ct power supply temperature sensor v ref ram neutral ian ibn pulse /aux spi interface host shunt ct or line vb resetz intz v 3p3a v 3p3sys MAX71020 resistor- divider line note: this system is referenced to line
19 MAX71020 single-chip electricity meter afe metrology temperature compensation voltage reference precision since the vref bandgap amplifier is chopper-stabilized the dc offset voltage, which is the most significant long- term drift mechanism in the voltage references, is auto - matically removed by the chopper circuit. maxim trims the vref voltage reference during the device manufac - turing process to ensure the best possible accuracy. the reference voltage (vref) is trimmed to a target value of 1.205v nominal. during this trimming process, the trimt[7:0] value is stored in nonvolatile fuses. trimt[7:0] is trimmed to a value that results in minimum vref variation with temperature. the trimt[7:0] value can be read by the host micro - controller during initialization to calculate parabolic tem - perature compensation coefficients suitable for each individual device. the resulting temperature coefficient for vref is 40ppm/c. considering the factory calibration temperature of vref to be +22c and the industrial temperature range (-40c to +85c), the vref error at temperature extremes can be calculated as: (85c - 22c) x 40ppm/c = +2520ppm = +1.252% and (-40c - 22c) x 40ppm/c = +2480ppm = -0.248% the above calculation implies that both the voltage and the current measurements are individually subject to a theoretical maximum error of approximately 0.25%. when the voltage sample and current sample are mul - tiplied together to obtain the energy per sample, the voltage error and current error combine resulting in approximately 0.5% maximum energy measurement error. however, this theoretical 0.5% error considers only the voltage reference (vref) as an error source. in practice, other error sources exist in the system. the principal remaining error sources are the current sensors (shunts or cts) and their corresponding signal condi - tioning circuits, and the resistor voltage-divider used to measure the voltage. the 0.5% grade devices should be used in class 1% designs, allowing sufficient margin for the other error sources in the system. crystal oscillator the oscillator drives an at cut microprocessor crystal at a frequency of 9.8304mhz. board layouts with minimum capacitance from xin to xout require less current. good layouts have xin and xout shielded from each other and from digital signals. since the oscillator is self-biasing, an external resistor must not be connected across the crystal. meter calibration once the MAX71020 energy meter device has been installed in a meter system, it must be calibrated. a com - plete calibration includes the following: establishment of the reference temperature (e.g., typi - cally 22 n c). calibration of the metrology section, i.e., calibration for tolerances of the current sensors, voltage-dividers, and signal conditioning components as well as of the internal reference voltage (vref) at the reference temperature (e.g., typically 22 n c). the metrology section can be calibrated using the gain and phase adjustment factors accessible to the ce. the gain adjust ment is used to compensate for tolerances of components used for signal conditioning, especially the resistive components. phase adjustment is provided to compensate for phase shifts introduced by the current sensors or by the effects of reactive power supplies. the MAX71020 supports common industry-standard cali - bration techniques, such as single-point (energy-only) and multipoint (energy, v rms , i rms ).
20 MAX71020 single-chip electricity meter afe host microcontroller interface register map table 7. register map name byte address r/w default value description cal_ia 0x010 r/w 0x0000 4000 calibration constant for current channel a. unity gain = 0x0000 4000. cal_va 0x011 r/w 0x0000 4000 calibration constant for current channel b. unity gain = 0x0000 4000. adj_a 0x012 r/w 0x0000 0000 cal_ib 0x013 r/w 0x0000 4000 calibration constant for voltage channel a. unity gain = 0x0000 4000. cal_vb 0x014 r/w 0x0000 4000 calibration constant for voltage channel b. unity gain = 0x0000 4000. adj_b 0x015 r/w 0x0000 0000 ceconfig 0x020 r/w 0x0030 db00 configures internal ce operation bit name description 0 pulse_slow reduces pulse output rate by a factor of 64. must not be used with pulse_fast. 1 pulse_fast increases pulse output rate by a factor of 16. must not be used with pulse_slow. 5:2 reserved 6 freqsel select phase for frequency measurement: 0 = a, 1 = b 7 reserved 19:8 sag_cnt number of consecutive voltage samples below sag_thr before a sag event is declared 20 sag_int enable sag detect output on ypulse 21 edge_int enable zero-crossing output on xpulse 31:22 reserved wrate 0x021 r/w 0x0000 0223 sets meter constant for pulse outputs. see the pulse generation section. kvar 0x022 r/w 0x0000 192c scale factor for var measurements sag_thr 0x024 r/w 0x016c af60 voltage threshold for sag warnings. see the ce status and control section. quant_va 0x025 r/w 0x0000 0000 truncation/noise compensation for voltage phase a quant_ia 0x026 r/w 0x0000 0000 truncation/noise compensation for current phase a quant_a 0x027 r/w 0x0000 0000 truncation/noise compensation for real power phase a quant_vara 0x028 r/w 0x0000 0000 truncation/noise compensation for reactive power phase a quant_vb 0x029 r/w 0x0000 0000 truncation/noise compensation for voltage phase b quant_ib 0x02a r/w 0x0000 0000 truncation/noise compensation for current phase b quant_b 0x02b r/w 0x0000 0000 truncation/noise compensation for real power phase b quant_varb 0x02c r/w 0x0000 0000 truncation/noise compensation for reactive power phase b gain_adj0 0x040 r/w 0x0000 4000 scale value for voltage inputs va and vb. default value of 16,384 is unity gain.
21 MAX71020 single-chip electricity meter afe table 7. register map (continued) name byte address r/w default value description gain_adj1 0x041 r/w 0x0000 4000 scale value for current input ia. default value of 16,384 is unity gain. gain_adj2 0x042 r/w 0x0000 4000 scale value for current input ib. default value of 16,384 is unity gain. wpulse_ctr 0x045 r pulse generator counter (real power) wpulse_frac 0x046 r pulse generator numerator (real power) wsum_accum 0x047 r pulse generator rollover accumulator (real power) vpulse_ctr 0x049 r pulse generator counter (reactive power) vpulse_frac 0x04a r pulse generator numerator (reactive power) vsum_accum 0x04b r pulse generator rollover accumulator (reactive power) cestatus 0x080 r - status of the compute engine bit name description 0 sag_a sag status, voltage phase a 1 sag_b sag status, voltage phase b 2 reserved - 3 f0 square wave at exact line frequency 31:4 reserved - freq_x 0x082 r fundamental line frequency in units of (2520.6 x 2 -32 )hz mainedge_x 0x083 r number of zero crossings of either direction during previous accumulation period wsum_x 0x084 r signed sum of real energy from both wattmeter elements w0sum_x 0x085 r real energy from wattmeter element 0 w1sum_x 0x086 r real energy from wattmeter element 1 varsum_x 0x088 r signed sum of reactive energy from both wattmeter elements var0sum_x 0x089 r reactive energy from wattmeter element 0 var1sum_x 0x08a r reactive energy from wattmeter element 1 i0sqsum_x 0x08c r sum of squared samples from current sensor 0 i1sqsum_x 0x08d r sum of squared samples from current sensor 1 v0sqsum_x 0x090 r sum of squared samples from voltage sensor 0 v1sqsum_x 0x091 r sum of squared samples from voltage sensor 1 ia 0x100 r most recent result of adc conversion for current channel a ib 0x102 r most recent result of adc conversion for current channel b vb 0x109 r most recent result of adc conversion for voltage channel b va 0x10a r most recent result of adc conversion for voltage channel a
22 MAX71020 single-chip electricity meter afe table 7. register map (continued) name byte address r/w default value description deviceid 0x301 r 0x0000 1100 contains identifying information for the device bit name description 7:0 reserved 15:8 version version index. currently, on 0x11 is defined as die type am48a0a. 31:16 chip_id family tag and feature tag of the device, currently 0x0000 stemp 0x30a r result of the temperature measurement. only bits 26:16 are significant; all other bits return zero. bsense 0x30b r result of the device v dd measurement. only bits 23:16 are significant; all other bits return zero.
23 MAX71020 single-chip electricity meter afe table 7. register map (continued) name byte address r/w default value description iocfg 0x30c r/w 0x0000 0f00 contains the characteristics of the four digital i/o pins bit name description 0 di0 reflects logic state on dio0 1 di1 reflects logic state on dio1 2 di2 reflects logic state on dio2 3 di3 reflects logic state on dio3 7:4 reserved 8 d_od0 configures dio0 as open drain if configured as output 9 d_od1 configures dio1 as open drain if configured as output 10 d_od2 configures dio2 as open drain if configured as output 11 d_od3 configures dio3 as open drain if configured as output 15:12 reserved 17:16 do configures dio0. 00: hi-z 01: wpulse 10: logic 1 11: logic 0 19:18 d1 configures dio1. 00: hi-z 01: vpulse 10: logic 1 11: logic 0 21:20 d2 configures dio2. 00: hi-z 01: xpulse 10: xfer_busy 11: logic 0 23:22 d3 configures dio3. 00: hi-z 01: ypulse 10: ce_busy 11: logic 31:24 reserved meter_cfg 0x30d r/w 0xff00 0080 configures hardware aspects of the afe bit name description 14:0 reserved 15 pls_inv force meter pulses to be positive-going rather than negative-going 23:16 reserved 31:24 pls_maxwid determines the maximum width of a meter pulse
24 MAX71020 single-chip electricity meter afe table 7. register map (continued) name byte address r/w default value description int_cfg 0x30f r/w 0x0000 8000 interrupt configuration register: configure the behavior of the intz pin bit name description 0 ie_wpulse enables an interrupt to occur on the leading edge of wpulse 1 ie_vpulse enables an interrupt to occur on the leading edge of vpulse 2 ie_ypulse enables an interrupt to occur on the leading edge of ypulse 3 ie_xpulse enables an interrupt to occur on the leading edge of xpulse 4 ie_xdata enables an interrupt to occur at the conclusion of the accumulation interval, indicating that fresh data is available 5 ie_cebusy enables an interrupt to occur when the ce cycles is complete 6 reserved 7 ie_vstat enables an interrupt to occur when the vsys status changes 11:8 int_pol interrupt polarity for the pulse edges. the default polarity is falling edge. int_pol[3]=1: interrupt on rising edge of ypulse int_pol[2]=1: interrupt on rising edge of xpulse int_pol[1]=1: interrupt on rising edge of vpulse int_pol[0]=1: interrupt on rising edge of wpulse 14:12 reserved 15 d_odintz enable open-drain on the intz output. by default, the pin is configured as a cmos totem- pole output. 31:16 reserved
25 MAX71020 single-chip electricity meter afe table 7. register map (continued) name byte address r/w default value byte address m_stat 0x310 r 0x0100 0100 reflects the status of several asynchronous events in the afe bit name description 0 f_wpulse set on start of wpulse 1 f_vpulse set on start of vpulse 2 f_xpulse set on start of ypulse 3 f_ypulse set on start of xpulse 4 f_xdata set when data available 5 f_cebusy set at end of ce code pass 6 reserved 7 f_vstat set when vsys status changes 8 f_reset set following afe reset 15:9 reserved 16 f_wpulse copy of bit 0 17 f_vpulse copy of bit 1 18 f_xpulse copy of bit 2 19 f_ypulse copy of bit 3 20 f_xdata copy of bit 4 21 f_cebusy copy of bit 5 23:22 reserved 24 f_reset copy of bit 8 31:25 reserved
26 MAX71020 single-chip electricity meter afe table 7. register map (continued) name byte address r/w default value description m_stat_b 0x311 r 0x0100 0100 backup of m_stat C updated when m_stat is read bit name description 0 fb_wpulse set on start of wpulse 1 fb_vpulse set on start of vpulse 2 fb_xpulse set on start of ypulse 3 fb_ypulse set on start of xpulse 4 fb_xdata set when data available 5 fb_cebusy set at end of ce code pass 7:6 reserved 8 fb_reset set following afe reset 15:9 reserved 16 fb_wpulse copy of bit 0 17 fb_vpulse copy of bit 1 18 fb_xpulse copy of bit 2 19 fb_ypulse copy of bit 3 20 fb_xdata copy of bit 4 21 fb_cebusy copy of bit 5 23:22 reserved 24 fb_reset copy of bit 8 31:25 reserved vstat 0x312 r afe supply voltage status. bits 1:0 reflect system power status: 00: system power-ok: v v3p3a > 3.0v 01: system power-low: 2.8v < v v3p3a < 3.0v 11: system power-fail: v v3p3a < 2.8v reset 0x322 wo write 0x8100 0000 to this register to reset the afe.
27 MAX71020 single-chip electricity meter afe table 7. register map (continued) name byte address r/w default value description temp_cnf 0x323 r/w 0x0000 0000 configures aspects of the temperature measurement subsystem bit name description 1:0 reserved 3:2 temp_per sets the period between temperature measurements. 01: measure every accumulation cycle 10: continuous measurement other values disable automatic updates. 4 temp_sys when set, vsys is measured at every temperature measurement cycle 31:5 reserved temp_start 0x324 r/w 0x0000 0000 write 0x8000 0000 to start a temperature conversion cycle. when conversion is complete, the afe will clear bit 31 and return the register to zero. spi_safe 0x325 r/w 0x0000 0000 write 0x8000 0000 to this word to lock the spi port. when the spi port is locked, no read or write operations are possible except to the spi_safe register. clearing this register to zero disables the spi lock and restores normal operation. meter_en 0x326 r/w 0x0000 0000 enables aspects of the afe bit name description 0 adc_e enable adc and vref buffer. must be set by host following initialization. 1 ce_e enable ce. must be set by host following initialization. 31:2 reserved
28 MAX71020 single-chip electricity meter afe ce interface description the ce reads the adc and stores its results in the 1kb block at 0x000. since all ce operations are 32 bits wide, the ce data memory occupies the first 256 32-bit loca - tions, from 0x000 to 0x0ff. note: the ce interface described in the data sheet is a description of a ce codebase that was available at the time of the writing. changes may have occurred in the codebase in the interim, and may not be reflected in this document. please contact your representative or maxim technical support for the latest information. ce data format all ce words are 4 bytes. unless specified other - wise, they are in 32-bit twos complement format (-1 = 0xffffffff). calibration para meters are copied to ce data memory by the host microcontroller before enabling the ce. internal variables are used in internal ce calcula - tions. input variables allow the mpu to control the behav - ior of the ce code. constants constants used in the ce data memory tables are: u f 0 is the fundamental frequency of the mains phases. u i max is the external rms current corresponding to the maximum allowed voltage on the current inputs. for the ib input, this is 250mv peak (176.8mv rms ). in the MAX71020, ia normally has a preamplifier enabled on the ia inputs, so i max needs to be adjusted to 27.78mv peak (19.64mv rms ) for the iap-ian inputs. for a 250? shunt resistor, i max becomes 78a (19.64mv rms /250? = 78.57a) for ia, and 707a (176.8mv rms /250? = 707.2a rms ) for ib. u v max is the external rms voltage corresponding to 250mv peak at the va and vb inputs. u n acc , the accumulation count for energy measure - ments (typically 2520). u the duration of the accumulation interval for energy measurements is n acc /f s = 2520/2,520.6 1s. u x is a gain constant of the pulse generators. its value is determined by pulse_fast and pulse_ slow(see table 13). u voltage lsb (for sag threshold) = v max x 7.879810 - 9v. the system constants i max and v max are used by the host processor to convert internal digital quantities (as used by the ce) to external, real-world metering quanti - ties. their values are determined by the scaling of the voltage and current sensors used in an actual meter. the lsb values used in this document relate digital quanti - ties at the ce or mpu interface to external meter input quantities. for example, if a sag threshold of 80v rms is desired at the meter input, the digital value that should be programmed into sag_thr (register 0x024) would be 80v rms x sqrt(2)/sag_thr lsb , where sag_thr lsb is the lsb value in the description of sag_thr (see table 14). environment before starting the ce (that is, before setting the ce_e bit) the host processor must establish the equation to be applied in equ[2:0]. by default, default settings are assumed to be v max = 600v, i max = 707a, and kh = 1. ce calculations in table 8 , the mpu selects the desired equation by writ - ing the equ[2:0] (register 0x30d[14:12]). table 8. ce equ equations and element input mapping equ watt and var formula (wsum/varsum) inputs used for energy/current calculation w0sum/ var0sum w1sum/ var1sum i0sq sum i1sq sum 0 va ia C 1 element, 2w 1 va x ia va x ib ia 1 va x (ia-ib)/2 C 1 element, 3w 1 va x (ia-ib)/2 ia-ib ib 2 va x ia + vb x ibC 2 element, 3w 1 va x ia vb x ib ia ib
29 MAX71020 single-chip electricity meter afe table 9. ce raw data access locations table 10. cestatusregister table 11. cestatus (register 0x080) bit definitions ce front-end data (raw data) access to the raw data provided by the afe is possible by reading registers 0x100C0x003 as shown in table 9 . ce status and control the ce status word, cestatus, is useful for generat - ing early warnings to the host processor ( table 10). it contains sag warnings for phase a and b, as well as f0, the derived clock operating at the line fre quency. the host microcontroller can read the ce status word at every ce_busy interrupt. cestatus provides information about the status of volt - age and input ac signal frequency, which are useful for generating an early power-fail warning to initiate neces - sary data storage. cestatus represents the status flags for the preceding ce code pass (ce_busy interrupt). the significance of the bits in cestatus is shown in table 11. pin register ia 0x100 va 0x101 ib 0x102 vb 0x103 ce address name description 0x80 cestatus see the description of cestatus bits in table 11 cestatus bit name description 31:4 not used these unused bits are always zero 3 f0 f0 is a square wave at the line frequency 2 not used this unused bit is always zero 1 sag_b set when vb remains below sag_thr for sag_cnt samples. automatically clears when vb rises above sag_thr. 0 sag_a set when va remains below sag_thr for sag_cnt samples. automatically clears when va rises above sag_thr.
30 MAX71020 single-chip electricity meter afe the ce is initialized by the host microcontroller using ceconfig ( table 12). this register contains the sag_cnt, freqsel[1:0], pulse_slow, and pulse_fast fields. the ceconfig bit definitions are given in table 13. the freqsel[1:0] field in ceconfig (register 0x020[7:6]) selects the phase that is utilized to generate a sag interrupt. thus, a sag_int event occurs when the selected phase has satisfied the sag event criteria as set by sag_thr (register 0x24) and the sag_cnt field in ceconfig (register 0x020[19:8]). when the sag_int bit (register 0x020[20]) is set to 1, a sag event gener - ates a transition on the ypulse output. in a two-phase system, and after a sag interrupt, the host microcontroller should change the freqsel[1:0] setting to select the other phase, if it is powered. even though a sag interrupt is only generated on the selected phase, both phases are simultaneously checked for sag. the presence of power on a given phase can be sensed by directly checking the sag_a and sag_b bits in cestatus (reg - ister 0x080[1:0]). the ce controls the pulse rate based on wsum_x (reg - ister 0x084) and varsum_x (register 0x088). table 12. ceconfig register table 13. ceconfig bit definitions ce address name data description 0x20 ceconfig 0x0030db00 see the description of the ceconfig bits in table 13 ceconfig bit name default description 21 edge_int 1 when 1, xpulse produces a pulse for each zero-crossing of the mains phase selected by freqsel[1:0] that can be used to interrupt the host microcontroller 20 sag_int 1 when 1, activates ypulse output when a sag condition is detected 19:8 sag_cnt 252 (0xfc) the number of consecutive voltage samples below sag_thr (register 0x24) before a sag alarm is declared. the default value is equivalent to 100ms 7:6 freqsel[1:0] 0 freqsel[1:0] selects the phase to be used for the frequency monitor, sag detection, and for the zero-crossing counter (mainedge_x, register 0x083) freq sel[1:0] phase selected 0 0 a 0 1 b 1 x not allowed 5:2 reserved 0 reserved 1 pulse_fast 0 when pulse_fast = 1, the pulse generator input is increased 16x. when pulse_slow = 1, the pulse generator input is reduced by a factor of 64. these two parameters control the pulse gain factor x (see table below). allowed values are either 1 or 0. default is 0 for both (x = 6). pulse_fast pulse_slow x 0 pulse_slow 0 0 0 1.5 x 2 2 = 6 1 0 1.5 x 2 6 = 96 0 1 1.5 x 2 -4 = 0.09375 1 1 do not use
31 MAX71020 single-chip electricity meter afe ce transfer variables when the host microcontroller receives the xfer_busy interrupt, it knows that fresh data is available in the trans - fer variables. ce transfer variables are modified during the ce code pass that ends with an xfer_busy inter - rupt. they remain constant throughout each accumula - tion interval. in this data sheet, the names of ce transfer variables always end with _x. the transfer variables can be categorized as: u fundamental energy measurement variables u instantaneous (rms) values u other measurement parameters fundamental energy measurement variables table 15 describes each transfer variable for fundamen - tal energy measurement. all variables are signed 32-bit integers. accumulated variables such as wsum are internally scaled so that internal values are no more than 50% of the full-scale range when the integration time is one second. additionally, the hardware does not permit output values to fold back upon overflow. wsum_x (register 0x084) and varsum_x (register 0x088) are the signed sum of phase-a and phase-b wh or varh values according to the metering equation spec - ified in equ[2:0](register 0x30d[14:12]). wxsum_x (x = 0 or 1, registers 0x085 and 0x086) is the watt-hour value accumulated for phase x in the last accumulation interval and can be computed based on the specified lsb value. table 14. sag threshold and gain adjust control table 15. ce transfer variables rms 9 max v2 sag_thr v 7.8798 10 ? = ce address name default description 0x24 sag_thr 2.39 x 10 7 the voltage threshold for sag warnings. the default value is equivalent to 113vpk or 80v rms if v max = 600v rms . 0x40 gain_adj0 16384 this register scales the voltage measurement channels va and vb. the default value of 16384 is equivalent to unity gain (1.000). 0x41 gain_adj1 16384 this register scales the ia current channel for phase a. the default value of 16384 is equivalent to unity gain (1.000). 0x42 gain_adj2 16384 this register scales the ib current channel for phase b. the default value of 16384 is equivalent to unity gain (1.000). ce address name description configuration 0x84 wsum_x the signed sum: w0sum_x + w1sum_x. not used for equ[2:0] = 0 (register 0x30d[14:12]) and equ[2:0] = 1. figure 8 0x85 w0sum_x the sum of wh samples from each wattmeter element. lsb w = 6.08040 x 10 -13 x v max x i max wh 0x86 w1sum_x 0x88 varsum_x the signed sum: var0sum_x + var1sum_x. not used for equ[2:0] = 0 and equ[2:0] = 1. 0x89 var0sum_x the sum of varh samples from each wattmeter element. lsb w = 6.08040 x 10 -13 x v max x i max varh 0x8a var1sum_x
32 MAX71020 single-chip electricity meter afe instantaneous energy measurement variables i_sqsum_x and v_sqsum (see table 16) are the sum of the squared current and voltage samples acquired during the last accumulation interval. the rms values can be computed by the host microcon - troller from the squared current and voltage samples as follows: i rms acc i_sqsum lsb 9,074,160 i n = other v rms acc v_sqsum lsb 9,074,160 v n = other transfer variables include those available for frequency and those reflecting the count of the zero- crossings of the mains voltage. these transfer variables are listed in table 17. mainedge_x (register 0x083) reflects the number of half-cycles accounted for in the last accumulated inter - val for the ac signal of the phase specified in the freqsel[1:0] field in ceconfig (register 0x020[7:6]). mainedge_x is useful for implementing a real-time clock based on the input ac signal. pulse generation table 18 describes the ce pulse generation parameters. the combination of the ceconfig:pulse_slow and ceconfig:pulse_fast bits (register 0x020[0:1]) con - trols the speed of the pulse rate. the default zero values of these configuration bits maintain the original pulse rate given by the kh equation, follows in this section. wrate (register 0x021) controls the number of pulses that are generated per measured wh and varh. the lower wrate is, the slower the pulse rate for the mea - sured energy quantity; or conversely, the greater the measured energy per pulse. by default, the pulse gener - ators take their input from the w0sum_x (register 0x085) and var0sum_x (register 0x089) result registers. the meter constant kh is derived from wrate and rep - resents the amount of energy measured for each pulse. if kh = 1wh/pulse and 120v and 30a is applied in-phase to the meter, the meter will produce one pulse per second (120v and 30a results in a load of 3600w, or put another way, energy consumption of one watt-hour per second). if the load is 240v at 150a, ten pulses per second are generated. to compute the wrate value, see table 18. the maximum pulse rate is 7.56khz. table 17. other transfer variables table 16. ce energy measurement variables ce address name description configuration 0x8c i0sqsum_x the sum of squared current samples from each element. lsb i = 6.08040 x 10 -13 imax 2 a 2 h when equ = 1, i0sqsum_x is based on ia and ib. figure 8 0x8d i1sqsum_x 0x90 v0sqsum_x the sum of squared voltage samples from each element. lsb v = 6.08040 x 10 -13 vmax 2 v 2 h 0x91 ? v1sqsum_x ce address name description 0x82 freq_x fundamental frequency: 0x83 mainedge_x the number of edge crossings of the selected voltage in the previous accumulation interval. edge crossings are either direction and are debounced. -6 32 2520.6hz lsb 0.509 10 2 ?
33 MAX71020 single-chip electricity meter afe see the vpulse and wpulse section for details on how to adjust the timing of the output pulses. the maximum time jitter is 1/6 of the multiplexer cycle period (nomi - nally 67s) and is independent of the number of pulses measured. thus, if the pulse generator is monitored for one second, the peak jitter is 67ppm. after 10s, the peak jitter is 6.7ppm. the average jitter is always zero. if it is attempted to drive either pulse generator faster than its maximum rate, it simply outputs at its maximum rate without exhibiting any rollover characteristics. the actual pulse rate, using wsum as an example, is: s 46 wrate wsum f x rate hz 2 = where f s = sampling frequency (2520.6hz), x = pulse speed factor derived from the ce variables pulse_slow (register 0x020[0]) and pulse_fast (register 0x020[1]). other ce parameters table 19 shows the ce parameters used for suppression of noise due to scaling and truncation effects. ce calibration parameters table 20 lists the parameters that are typically entered to effect calibration of meter accuracy. ce flow diagrams figure 10 to figure 12 show the data flow through the ce in simplified form. functions not shown include delay compensation, sag detection, scaling, and the process - ing of meter equations. table 18. ce pulse generation parameters ce address name default description 0x21 wrate 547 where: k = 42.7868 see table 13 for the definition of x. the default value yields 1.0 wh/pulse for v max = 600v and i max = 208a. the maximum value for wrate is 32,768 (2 15 ). 0x22 kvar 6444 scale factor for var measurement 0x45 wpulse_ctr 0 wpulse counter 0x46 wpulse_frac 0 unsigned numerator, containing a fraction of a pulse. the value in this register always counts up towards the next pulse. 0x47 wsum_accum 0 rollover accumulator for wpulse 0x4a vpulse_ctr 0 vpulse counter 0x4a vpulse_frac 0 unsigned numerator, containing a fraction of a pulse. the value in this register always counts up towards the next pulse. 0x4b vsum_accum 0 rollover accumulator for vpulse max max kv i kh wh pulse sum_samps wrate x =
34 MAX71020 single-chip electricity meter afe table 19. ce parameters for noise suppression and code version table 20. ce calibration parameters ce address name default description 0x25 quant_va 0 compensation factors for truncation and noise in voltage, current, real energy, and reactive energy for phase a. 0x26 quant_ia 0 0x27 quant_a 0 0x28 quant_vara 0 0x29 quant_vb 0 compensation factors for truncation and noise in voltage, current, real energy, and reactive energy for phase b. 0x2a quant_ib 0 0x2b quant_b 0 0x2c quant_varb 0 -13 2 2 max quant_ix_lsb 3.28866 10 i (amps ) = -10 max max quant_wx_lsb 6.73518 10 v i (watts) = -10 max max quant_varx_lsb 6.73518 10 v i (vars) = ce address name default description 0x10 cal_ia 16384 these constants control the gain of their respective channels. the nominal value for each parameter is 2 14 = 16384. the gain of each channel is directly proportional to its cal parameter. thus, if the gain of a channel is 1% slow, cal should be increased by 1%. 0x11 cal_va 16384 0x13 cal_ib 16384 0x14 cal_vb 16384 0x12 phadj_a 0 these constants control the ct phase compensation. compensation does not occur when phadj_x = 0. as phadj_x is increased, more compensation (lag) is introduced. the range is 215 C 1. if it is desired to delay the current by the angle f , the equations are: 20 0.02229 tan phadj_x 2 0.1487 - 0.0131 tan f = f at 60hz 20 0.0155 tan phadj_x 2 0.1241- 0.009695 tan f = f at 50hz 0x15 phadj_b 0
35 MAX71020 single-chip electricity meter afe figure 10. ce data flow (multiplexer and adc) figure 11. ce data flow (scaling, gain control, intermediate variables) multiplexer demultiplexer v ref i0 v0 i1 i0_raw v0_raw i1_raw dc mod decimator f clk = 4.9152mhz f s = 2520hz (on each channel) offset null offset null offset null f0 generator phase comp phase comp 90 lpf lpf w0 var0 i0 v0 i0_raw v0_raw f0 f0 cal_i0 phadj_0 i1_raw f0 cal_v0 cal_i1 gain_adj lpf w1 i1 f0 lpf var1 phadj_1
36 MAX71020 single-chip electricity meter afe package information for the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. ordering information figure 12. ce data flow (squaring and summation stages) note: all devices are specified over the -40c to +85c oper - ating temperature range. + denotes a lead(pb)Cfree/rohs-compliant package. part pin- package accuracy (%) packaging MAX71020aeui+ 28 tssop 0.5 bulk MAX71020aeui+r 28 tssop 0.5 tape and reel package type package code outline no. land pattern no. 28 tssop u28+1 21-0066 90-0171 i1 f0 i 2 square v0 v 2 i0 i 2 c sum c c iisq vosq iosq iisqsum_x vosqsum_x iosqsum_x sum_samps = 2520 w1 w0 sum mpu c w1sum_x w0sum_x var0 c c vas0sum_x var01 c var1sum_x
revision history revision number revision date description pages changed 0 7/12 initial release maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. the parametric values (min and max limits) shown in the electrical characteristics table are guaranteed. other parametric values quoted in this data sheet are provided for guidance. maxim integrated products, inc. 160 rio robles, san jose, ca 95134 usa 1-408-601-1000 37 ? 2012 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. MAX71020 single-chip electricity meter afe

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